1. Field of the Invention
The present invention relates to a pulse generator, in particular to a pulse generator for generating a pulse signal, which, as a circuit element, only occupies a small area by making use of a characteristic that the potential in both ends of a capacitor is maintained.
2. Description of the Background Art
In general, a Synchronous Dynamic Random Access Memory (SDRAM) is a memory device for controlling input/output of data synchronized with a clock (CLK) signal, in which internal pulse signals are generated regularly, thereby controlling input/output of data according to the CLK signal.
FIG. 1 is a view illustrating a conventional pulse generator.
Referring to FIG. 1, the pulse generator comprises a delay unit 1 for receiving an input signal Sin, delaying it by a certain time interval and then outputting the delayed signal as a delay signal D, and a NAND gate 2 for receiving the input signal Sin and the delay signal D applied from the delay unit 1. The NAND gate performs a NAND operation and then outputs a pulse signal Sout.
The delay unit 1 of FIG. 1 can be constructed as shown in FIGS. 2a or 2b. 
The delay unit 1, as shown in FIG. 2a, can be made by serially connecting an odd number of inverters IVO in order to delay the input signal Sin. The delay unit 1, as shown in FIG. 2a, may also be made by serially connecting an odd number of inverters IVO through the medium of a resistor R1 in order to delay the input signal Sin.
As shown in FIG. 3, a conventional pulse generator having the above-mentioned construction outputs a pulse signal Sout that is synchronized with a low level when the input signal Sin transitions from low to high.
FIG. 1 shows an example of generation of a pulse being synchronized with a rising time of the input signal Sin. Unlike this, a circuit for generating a pulse being synchronized with a falling time of the input signal Sin is disclosed in FIG. 4.
Referring to FIG. 4, the pulse generator comprises a delay unit 3 for receiving an input signal Sin, delaying it by a certain time interval and then outputting the delayed signal as a delay signal D, and an NOR gate 4 for receiving the input signal Sin and the delay signal D applied from the delay unit 1. The NOR gate performs a NOR operation and then outputting a pulse signal Sout.
As shown in FIG. 5, the conventional pulse generator having a construction as shown in FIG. 4, outputs a pulse signal Sout that is synchronized with a high level when the input signal Sin transitions from high to low.
According to the conventional pulse generator shown in FIGS. 1 and 4, the delay unit 1 has at least six or more transistors for constructing an odd number of inverters IVO. Also, the NAND gate 2 or NOR gate 4 consists of at least 2 transistors. Furthermore, the delay unit 1 has a plurality of capacitors or resistors for lengthening the delay time of the input signal Sin.
As a result, the conventional pulse generator has at least eight transistors and a plurality of capacitors or resistors. In general, the total number of the elements used for constructing the pulse generator sums between 14 and 18.
However, the conventional pulse generator as mentioned above has a disadvantage of occupying a large area when constructing a semiconductor memory device, because the pulse generator consists of many elements.
Accordingly, it is an object of the present invention to provide a pulse generator which generates a pulse signal by making use of a characteristic of a capacitor that a potential at both ends of the capacitor is maintained, thereby implementing a pulse generator in a small area.
In order to achieve the above-described object and one aspect of the present invention, a pulse generator comprises: a voltage level control means for controlling a voltage level of a first node according to the state of an input signal; a first switching means for controlling a voltage level of a second node, which is switched in accordance with the state of the input signal; a second switching means for changing the voltage level of the second node which is switched opposite to the first switching means according to the state of the input signal; a charge/discharge means for charging/discharging a voltage between the first node and the second node according to a switching state of the first and the second switching means; and an output means for outputting a pulse signal according to the charging/discharging state of the charge/discharge means.